FPGA Design Engineer

Company: Catapult Staffing
Location: Camden
Posted on: May 10, 2025

Job Description:

FPGA/ASIC Design Engineer

For a complete understanding of this opportunity, and what will be required to be a successful applicant, read on.
Location: On-site in Camden, NJ
Role Type: Contract (9/80 Schedule with 8am start time)
Clearance: Secret

About Our Client
Our client is a leading defense contractor specializing in advanced communication systems for national security applications. With decades of experience delivering mission-critical technologies, they have established themselves as a trusted partner to government agencies and defense organizations.
The company invests heavily in state-of-the-art Electronic Design Automation (EDA) tools and methodologies, including Synopsys DC/Primetime/Synplify, Xilinx/Intel/Microchip EDA including HLS, Mentor Questa family, VIPs for UVM, Clock Domain Crossing (CDC), and Catapult (HLS). They are committed to innovation, excellence, and maintaining the highest standards of security and reliability in their products, which play a vital role in protecting national interests.

Job Description
As an FPGA/ASIC Design Engineer, you will be responsible for the architecture, implementation, and verification/validation of complex FPGA and/or ASIC systems through software integration testing. This is a high-impact, high-visibility role that directly contributes to the delivery of communication products essential for national security.
Your day-to-day work will involve developing architectures for high-throughput complex designs involving cryptographic algorithms (VHDL) with high-speed protocols such as NVMe, PCIe/SRIOV, 10G-400G Ethernet, TCP/IP, and IP development/integration targeting ARM SOC FPGAs (e.g., Xilinx MPSOC) and/or ASICs. You will also write and debug tests and sequences for end-to-end simulation on UVM framework with System Verilog Assertions, as well as C++ based software-driven validation on SOC evaluation boards (Xilinx MPSOC) running Linux.
The ideal candidate is passionate about digital design, has excellent analytical and debugging skills, and is committed to delivering robust, high-quality solutions for critical national security applications. You will collaborate with cross-functional teams including software engineers, systems engineers, and program managers to ensure successful product delivery.

Duties and Responsibilities Develop architectures for implementing high-throughput complex designs with cryptographic algorithms in VHDL. Implement designs utilizing high-speed protocols such as NVMe, PCIe/SRIOV, 10G-400G Ethernet, and TCP/IP. Perform IP development and integration targeting ARM SOC FPGAs (e.g., Xilinx MPSOC) and/or ASICs. Write and debug tests/sequences for end-to-end simulation on UVM framework with System Verilog Assertions. Develop and debug C++ based software-driven validation on SOC evaluation boards running Linux. Utilize state-of-the-art EDA tools and methodologies for design implementation and verification. Collaborate with cross-functional teams to ensure successful product delivery and integration. Perform rigorous testing and validation to ensure designs meet performance, power, and area requirements. Document design specifications, test procedures, and validation results. Stay current with emerging technologies and methodologies in FPGA/ASIC design.














Required Experience/Skills Bachelor of Science in Electrical Engineering or Computer Science or equivalent (Master's degree preferred). Minimum 3 years of experience with proven track record implementing complex algorithms targeting ASICs/FPGAs. Proficiency in VHDL and FPGA design/debug with Xilinx FPGA / Vivado. Excellent analytical and debugging skills for complex digital systems. Strong verbal, written, and presentation skills for effective communication. Ability to work in a team environment while also being self-directed.







Nice-to-Haves Prior experience with High Level Synthesis (HLS) with Vivado. Knowledge of Embedded Software C++ (OOP). Experience with System Verilog Assertions (SVA). Familiarity with high-speed protocols (PCIe, TCP/IP, Ethernet). Experience with UVM-based verification environments. Knowledge of ARM-based SoC architectures. Master of Science in Electrical Engineering or Computer Science. Experience with ASIC design and verification methodologies.









Education
Bachelor of Science in Electrical Engineering or Computer Science or equivalent required.
Master of Science in Electrical Engineering or Computer Science preferred.

Pay & Benefits Summary Competitive salary commensurate with experience and education. Comprehensive benefits package including medical, dental, and vision insurance. 401(k) retirement plan with company matching. Flexible 9/80 work schedule (9-hour days with every other Friday off). Paid time off and company holidays. Professional development and continuing education opportunities. Potential for career advancement in a growing organization. Relocation assistance may be available for qualified candidates.










Join our team of talented engineers working on cutting-edge FPGA and ASIC designs for critical national security applications. Apply today to contribute to technology that makes a difference!

Keywords: FPGA Engineer - ASIC Design - VHDL - Xilinx - Digital Design - Defense - UVM - Cryptographic - High Speed Protocols - SOC - Embedded Systems - National Security

Keywords: Catapult Staffing, Philadelphia , FPGA Design Engineer, Engineering , Camden, Pennsylvania